Digital frequency synthesis processes have been developed for producing variable frequency sinusoids and for generating variable frequency pulse trains or "clocks." See, for example, Tierney, J., "Digital Frequency Synthesizers," Frequency Synthesis: Techniques and Applications, Edited by J. Gorski-Popiel, IEEE Press, 1975, pp. 121-149. Although there are conceptual similarites among these processes, there are significant functional and implementational differences between them, so the following discussion will focus on clock frequency synthesizers.
Some variable clock frequency synthesizers operate by dividing a time dependent factor, N, into a stable reference clock frequency, f.sub.r, thereby generating an output clock at a frequency f.sub.o, which is given for any specific value of N by: EQU f.sub.o =f.sub.1 /N (1)
These divider-type synthesizers typically are relatively simple and inexpensive because the divide function can be performed by a counter which issues a single output pulse for each sequence of N reference pulses counted. Unfortunately, however, they are handicapped by the inversely proportional relationship of their output clock frequency, f.sub.o, to the value of their frequency controlling variable, N. That limits their utility, not only by causing them to have non-linear frequency resolutions, but also by concentrating the great majority of their frequency generating capacity (i.e., the frequencies which are more finely resolveable) at the lower end of their output frequency spectra.
Arithmetic variable clock frequency synthesizers inherently have linearly resolveable output frequency spectra, so they generally are favored for applications calling for broad band frequency control. Such a synthesizer conventionally includes an accumulator for recursively accumulating a binary word of predetermined bit length, R, and time dependent value, N, at a stable reference clock frequency, f.sub.r. Consequently, the most significant bit (MSB) of the word accumulated by the accumulator oscillates at a variable clock frequency, f.sub.o, which is given for any specific value of N within the range -2.sup.R-1 .ltoreq.N&lt;.sub.2.sup.R-1 by: EQU f.sub.o =f.sub.r (N/2.sup.R-1) (2)
Equation (2) suggests that the length, R, of the word being accumulated may be increased to enhance resolution of this type of synthesizer. As a general rule, however, the maximum permissible reference frequency, f.sub.r(max), for an arithmetic frequency synthesizer drops as the length of its accumulator is increased because the time allowance that is required for all necessary carries to propogate sequentially from the least significant bit (LSB) to the MSB of the word being accumulated is directly dependent on the length of the word (i. e., the accumulatorlength).Therefore, designers of these synthesizers often have to make a difficult tradeoff decision between frequency resolution, on the one hand, and high frequency cut-off limit, f.sub.o(max), on the other.